1. Field of the Invention
This invention relates generally to increasing operational speed in an encryption domain.
2. Discussion of the Related Art
The document “RFC 1321-The MD5—Message-Digest Algorithm” by R. Rivest, MIT Laboratory for Computer Science and RSA Data Security, Inc., April 1992, pages 1-18, incorporated by reference herein, discloses an operational approach represented by the structure of FIG. 1. In such operation, register A is filled with data made up of 32 bits (A31, A30, . . . A0), register B is filled with data made up of 32 bits (B31, B30, . . . B0), register C is filled with data made up of 32 bits (C31, C30, . . . C0), and register D is filled with data made up of 32 bits (D31, D30, . . . D0). In addition, register 5 is filled with 512 bits of data, and register 6 is filled with 512 bits of data. Each of the bits in the registers A, B, C, D, 5, and 6 may have a value of 0 or 1.
In accordance with that paper, four auxiliary functions are defined:    F(B, C, D)=BC v not(B) D    G(B, C, D)=BD v C not(D)    H(B, C, D)=B xor C xor D    I(B, C, D)=C xor (B v not(D))
In addition, the 512 bits in the register 5 are broken down into 16 separate groups (k=0-15) of 32 bits each, and the function X(k) operates to select a group thereof determined by the value of k. The 512 bits in the register 6 are broken down into 16 separate groups (i=1-16) of 32 bits each, and the function T(i) operates to select a group thereof determined by with the value of i. The function CLS(s) rotator 11 operates to rotate the contents presented thereto by a number of bits determined by the value s (s=1-64).
With [ABCD k s i] denoting the operation for each of the following rounds:
/* Round 1. */   result = b + ((a + F(b,c,d) + X[k] + T[i]) <<< s). */ /* The following 16 operations are undertaken. */  [ABCD 07 1][DABC 112 2][CDAB 217 3][BCDA 322 4]  [ABCD 47 5][DABC 512 6][CDAB 617 7][BCDA 722 8]  [ABCD 87 9][DABC 91210][CDAB101711][BCDA112212]  [ABCD12713][DABC131214][CDAB141715][BCDA152216] /* Round 2. */   result = b + ((a + G(b,c,d) + X[k] + T[i]) <<< s). */ /* Do the following 16 operations. */  [ABCD 1517][DABC 6 918][CDAB111419][BCDA 02020]  [ABCD 5521][DABC10 922][CDAB151423][BCDA 42024]  [ABCD 9525][DABC14 926][CDAB 31427][BCDA 82028]  [ABCD13529][DABC 2 930][CDAB 71431][BCDA122032] /* Round 3. */   result = b + ((a + H(b,c,d) + X[k] + T[i]) <<< s). */ /* Do the following 16 operations. */  [ABCD 5433][DABC 81134][CDAB111635][BCDA142336]  [ABCD 1437][DABC 41138][CDAB 71639][BCDA102340]  [ABCD13441][DABC 01142][CDAB 31643][BCDA 62344]  [ABCD 9445][DABC121146][CDAB151647][BCDA 22348] /* Round 4. */   result = b + ((a + I(b,c,d) + X[k] + T[i]) <<< s). */ /* Do the following 16 operations. */  [ABCD 0649][DABC 71050][CDAB141551][BCDA 52152]  [ABCD12653][DABC 31054][CDAB101555][BCDA 12156]  [ABCD 8657][DABC151058][CDAB 61559][BCDA132160]  [ABCD 4661][DABC111062][CDAB 21563][BCDA 92164]
Referring to FIGS. 1 and 2, the first operation of the first round, i.e., [ABCD 0 7 1] will now be described.
Initially, the 32-bit data set in the register A is applied to the adder 7. The first variable of the data set of register B, i.e., the bit B31, the first variable of the data set in register C, i.e., the bit C31, and the first variable of the data set in register D, i.e., the bit D31 (first set of variables B31, C31, D31) are applied as inputs to the logic block 8, which can apply either the function F, G, H or I to these variables. At the same time, the second variable of the data set of register B, i.e., the bit B30, the second variable of the data set of register C, i.e., the bit C30, and the second variable of the data set of register D, i.e., the bit D30 (second set of variables B31, C31, D31) are also applied as inputs to the logic block 8, etc., for each of the sets of variables. In this particular case, the function F is applied to these variables (FIG. 2). The process is run in parallel on each of the 32 sets of three bits, generating a 32-bit output which is applied to the adder 7. With application of the 32-bit output from the logic block 8 to the adder 7, the contents of the register B are applied to the register C and to the adder 12, the contents of the register C are applied to the register D, and the contents of register D are applied to register A. The input from the logic block 8 and the data set of register A applied to the adder 7 are added by the adder 7, which provides a 32-bit output to adder 9. The value k=0 indicates that the 32-bit group 0 of the register 5 is applied as an input to the adder 9, and the input from the adder 7 and the 32-bit group 0 of the register 5 are added by the adder 9. The output of the adder 9 is applied to adder 10, and the value i=1 indicates that the 32-bit group 1 of the register 6 is applied as an input to the adder 10, and the input from the adder 9 and the 32-bit group 1 of register 6 are added by the adder 10. The 32-bit output from the adder 10 is rotated by the rotator CLS(s) 11 as determined by the number s, in this case, s=7. The rotated contents are applied to the adder 12, and are added to the contents of register B which have been applied to the adder 12. The output of the adder 12 is applied to the register B.
For the second operation of the first round, i.e., [DABC 1 12 2] the procedure is repeated, again applying the function F, and this procedure is repeated for all 16 operations of the first round, each of which applies the function F.
For the first operation of the second round, i.e., [ABCD 1 5 17], the above procedure is applied, however, with the logic block 8 applying the function G to the inputs provided thereto (FIG. 4). Similar to the above, 16 operations of the second round are undertaken in accordance with the above chart.
The third and fourth rounds are undertaken in like manner, using the function H (FIG. 5) and the function I (FIG. 6) respectively, again in accordance with the above chart.
As will be seen, the application of a function by the logic block 8 is dependent on inputs from registers B, C and D. While in each operation the contents of registers C and D are directly available to the logic block 8, after the first operation of the first round, the contents of register B to be applied to the logic block 8 are arrived at through a number of calculations involving adder 7, register 5, adder 9, adder 10, register 6, rotator 11, and adder 12. This time-consuming process causes the overall system to operate more slowly than is desired, since the logic block 8 must wait for inputs from all three registers B, C and D before applying the function thereof.
Therefore, what is needed is a method for speeding up the operation described above.